Mechanical and chemical-mechanical planarization processes ("CMP") are used in the manufacturing of electronic devices for forming a flat surface on semiconductor wafers, field emission displays and many other microelectronic-device substrate assemblies. CMP processes generally remove material from a substrate assembly to create a highly planar surface at a precise elevation in the layers of material on the substrate assembly. FIG. 1 schematically illustrates an existing web-format planarizing machine 10 for planarizing a substrate 12. The planarizing machine 10 has a support table 14 with a top-panel 16 at a workstation where an operative portion (A) of a planarizing pad 40 is positioned. The top-panel 16 is generally a rigid plate to provide a flat, solid surface to which a particular section of the planarizing pad 40 may be secured during planarization.
The planarizing machine 10 also has a plurality of rollers to guide, position and hold the planarizing pad 40 over the top-panel 16. The rollers include a supply roller 20, first and second idler rollers 21a and 21b, first and second guide rollers 22a and 22b, and take-up roller 23. The supply roller 20 carries an unused or pre-operative portion of the planarizing pad 40, and the take-up roller 23 carries a used or post-operative portion of the planarizing pad 40. Additionally, the first idler roller 21 a and the first guide roller 22a stretch the planarizing pad 40 over the top-panel 16 to hold the planarizing pad 40 stationary during operation. A motor (not shown) drives at least one of the supply roller 20 and the take-up roller 23 to sequentially advance the planarizing pad 40 across the top-panel 16. Accordingly, clean pre-operative sections of the planarizing pad 40 may be quickly substituted for used sections to provide a consistent surface for planarizing and/or cleaning the substrate 12.
The web-format planarizing machine 10 also has a carrier assembly 30 that controls and protects the substrate 12 during planarization. The carrier assembly 30 generally has a substrate holder 32 to pick up, hold and release the substrate 12 at appropriate stages of the planarizing process. Several nozzles 33 attached to the substrate holder 32 dispense a planarizing solution 44 onto a planarizing surface 42 of the planarizing pad 40. The carrier assembly 30 also generally has a support gantry 34 carrying a drive assembly 35 that translates along the gantry 34. The drive assembly 35 generally has an actuator 36, a drive shaft 37 coupled to the actuator 36, and an arm 38 projecting from the drive shaft 37. The arm 38 carries the substrate holder 32 via a terminal shaft 39 such that the drive assembly 35 orbits the substrate holder 32 about an axis B-B (as indicated by arrow R.sub.1). The drive assembly 35 can also rotate the substrate holder 32 about its central axis C-C (as indicated by arrow R.sub.2).
The planarizing pad 40 and the planarizing solution 44 define a planarizing medium that mechanically and/or chemically-mechanically removes material from the surface of the substrate 12. The planarizing pad 40 used in the web-format planarizing machine 10 is typically a fixed-abrasive planarizing pad in which abrasive particles are fixedly bonded to a suspension material. In fixed-abrasive applications, the planarizing solution is a "clean solution" without abrasive particles because the abrasive particles are fixedly distributed across the planarizing surface 42 of the planarizing pad 40. In other applications, the planarizing pad 40 may be a non-abrasive pad without abrasive particles, composed of a polymeric material (e.g., polyurethane) or other suitable materials. The planarizing solutions 44 used with the non-abrasive planarizing pads are typically CMP slurries with abrasive particles and chemicals to remove material from a substrate. Typical abrasive particles include ILD 1300 fumed silica particles, available from Rodel, Inc. of Wilmington, Del. and having a mean cross-sectional dimension of 200 nanometers, or Klebosol 1508-50 colloidal particles, also available from Rodel, Inc. and having a mean cross-sectional dimension of fifty nanometers.
To planarize the substrate 12 with the planarizing machine 10, the carrier assembly 30 presses the substrate 12 against the planarizing surface 42 of the planarizing pad 40 in the presence of the planarizing solution 44. The drive assembly 35 then orbits the substrate holder 32 about the axis B-B and/or rotates the substrate holder 32 about the axis C-C to translate the substrate 12 across the planarizing surface 42. As a result, the abrasive particles and/or the chemicals in the planarizing medium remove material from the surface of the substrate 12.
The CMP processes should consistently and accurately produce a uniformly planar surface on the substrate assembly to enable precise fabrication of circuits and photo-patterns. During the fabrication of transistors, contacts, interconnects and other features, many substrate assemblies develop large "step heights" that create a highly topographic surface across the substrate assembly. Yet, as the density of integrated circuits increases, it is necessary to have a planar substrate surface at several intermediate processing stages because non-uniform substrate surfaces significantly increase the difficulty of forming sub-micron features. For example, it is difficult to accurately focus photo patterns to within tolerances approaching 0.1 micron on non-uniform substrate surfaces because sub-micron photolithographic equipment generally has a very limited depth of field. Thus, CMP processes are often used to transform a topographical substrate surface into a highly uniform, planar substrate surface.
During one conventional process, capacitors and other electrical components are formed in the microelectronic substrate 12 by first forming an aperture in the substrate 12 and then depositing successive layers of conductive and dielectric materials into the aperture. For example, FIG. 2A is a cross-sectional view of a portion of the substrate 12 shown in FIG. 1. The substrate 12 includes a base dielectric material 50 having two capacitor apertures 51. The walls of the capacitor apertures 51 are initially coated with a first conductive layer 60 that extends between the adjacent apertures. The substrate 12 is then planarized, using a process such as that discussed above with reference to FIG. 1, to remove intermediate portions 56 from between the capacitor apertures 51. Accordingly, the remaining portions of the conductive layer 60 within each capacitor aperture 51 are electrically isolated from each other.
As shown in FIG. 2B, a layer of dielectric material 61 is deposited on the remaining portions of the conductive layer 60 and on the exposed portions of the substrate upper surface 54. A second conductive layer 62 is deposited on the dielectric material 61 to form capacitors 70. An insulating material 63, such as borophosphate silicon glass (BPSG) is disposed on the second conductive layer 62 to fill the remaining space in the capacitor apertures 51 and electrically insulate the capacitors 70 from additional structures subsequently formed on the substrate 12. After the capacitors 70 are formed, a conductive plug aperture 52 is etched into the substrate 12 and filled with a conductive material to provide a conductive path between layers of the substrate 12.
One potential problem with the conventional method described above with reference to FIGS. 1-2B is that the base dielectric material 50 can crack during the planarization process. For example, the base dielectric material 50 typically includes an oxide or glass, such as silicon dioxide or BPSG, both of which are generally brittle. As the intermediate portions 56 are removed from between adjacent capacitor apertures 51, cracks 53 may form in the base dielectric material 50 between the adjacent capacitor apertures 51 at or beneath the substrate upper surface 54. Alternatively, the cracks 53 may extend from one or more of the capacitor apertures 51 to the conductive plug aperture 52. In either case, when the substrate 12 is heated during subsequent processing steps, the first conductive layer 60 may soften and flow through the cracks 53, potentially forming short circuits between neighboring capacitors 70 or between the capacitors 70 and the conductive plug formed in the plug aperture 52. These short circuits can substantially impair the performance of the resulting microelectronic device.